1. Field of the Invention
The invention relates to a method for forming an integrated circuit, and more particularly, to a method for forming an intermetal dielectric layer with multilevel interconnects.
2. Description of the Related Art
In an integrated circuit with two or more levels of interconnects, an intermetal dielectric layer must be placed between the levels for isolation. Generally, the intermetal dielectric layer must have characteristics such as good reliability, good mechanical stability, good compatibility, low water absorption capability, etc.
A typical material for the intermetal dielectric layer is silicon oxide that has a dielectric constant of about 4. However, since a device having a higher operation speed requires a material having a lower dielectric constant as the intermetal dielectric layer, fluorinated silicon glass (FSG) having a dielectric constant of about 3.5 is replacing the silicon oxide as the intermetal dielectric layer.
According to the prior art, the method to form the intermetal dielectric layer is as follows. A plurality of metal conductive lines is formed on a substrate. The plurality of metal conductive lines is distributed in two regions, respectively, a tied conductive line region (i.e. a dense line region) having a higher distribution density and a loose conductive line region (i.e. a iso line region) having a lower distribution density. A biased-clamped FSG layer is formed on the substrate by high density plasma chemical vapor deposition (HDPCVD), and fills gaps between metal lines. Before the biased-clamped FSG layer is formed, the process further comprises forming a silicon glass liner layer by HDPCVD. The silicon glass liner layer is used to prevent the metal lines from being attacked by fluorine. Then, an oxide layer is formed as a cap layer on the biased-clamped FSG layer by plasma enhanced chemical vapor deposition (PECVD). A chemical mechanical polishing process is subsequently performed on the oxide layer.
Due to different distribution densities, the spacing between conductive lines in different regions (the tied conductive line region and the loose conductive line region) is different. This may result in a large step height difference between the tied conductive line region and the loose conductive line region after the biased-clamped FSG layer and the cap layer are formed. Thus, the polishing stop for chemical mechanical polishing is difficult to control, and over-polishing easily arises. As a result, the biased-clamped FSG layer may be exposed. Since the amount of fluorine in the biased-clamped FSG layer is difficult to control, and the biased-clamped FSG layer exhibits intrinsically hydrophilic behavior, the biased-clamped FSG layer easily absorbs water when the biased-clamped FSG layer contacts is in contact with an aqueous base slurry during chemical mechanical polishing process. Thus, the reaction product produced during chemical mechanical polishing process can result in metal corrosion, oxide degradation, peeling at the metal/intermetal dielectric layer interface, and an increased dielectric constant. Furthermore, when a metal plug is formed, the HF can poison the metal plug, the contact resistance is increased and the increased contact resistance can affect the subsequent process.